aki-nyan

abyssal witch | deranged catgirl hardware/software engineer + vtuber | that crazy SCSI girl | she/her

#nobot

Public Key

npub1vnmkvkfqas3h2ahtzndqaen5sa7j2e3smalw2axhjrprm0e267ysw8wd0z

NIP-05 Address

lethalbit@chaos-social.mostr.pub

Profile Code

nprofile1qqsxfamxtyswcgm4wm43fkswue6gwlf9vccd7lh9wnteps3ahu4d0zgpz3mhxue69uhhyetvv9ujuerpd46hxtnfduqs6amnwvaz7tmwdaejumr0dsukvkjm

Publishing to

relay.damus.io

nos.lol

Author Public Key

npub1vnmkvkfqas3h2ahtzndqaen5sa7j2e3smalw2axhjrprm0e267ysw8wd0z

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Last Notes

2026-10-27 05:30:29 UTC

I am thinking about moving from nixops to OpenTofu + Ansible,
I'm not familiar enough with either of them to know if it'll be able to fully replace it for me, but we'll see.
Would be nice to be able to do update/patch management centrally via thaat system as well, mmm...
Dunno!

2026-10-26 08:33:17 UTC

So, rather than doing the actual work I need to do, my now medicated brain is wiggly and wanting me to focus on other things that I really don't have the time or bw for....

2026-10-25 08:30:13 UTC

Question for my software engineering friends!
Which versioning scheme do you tend to like/use for your projects?
Do you go with something like strict semver? The Python versioning scheme?
Or maybe something like calver?
Something else? let me know! I would love to hear what you use and the reasoning!

2026-10-25 05:13:11 UTC

I know I'm technically my title for a project is "core contributor", but I think having it be set as "local catgirl" is better....

2026-10-21 07:29:45 UTC

Looking through the ISO 7000 symbols and came across "Do Not Pet Radio Tower" (Ref No. 6167)
https://assets.chaos.social/media_attachments/files/117/477/705/861/007/148/original/39d9b7d1817544e1.png

2026-10-21 06:35:06 UTC

I'm still slightly impressed and horrified at Intel for this monstrosity of an initialism
https://assets.chaos.social/media_attachments/files/117/477/503/169/280/056/original/51ea0ca5e11dde06.png

2026-10-20 21:21:51 UTC

once again very grumpy that Thunderbird filters don't let you do regex on them....
I want to make an email filter that lets me take:
from: codeberg.org
subject-contains: `^(RE:)?\[([a-zA-Z0-9_-]+)\/([a-zA-Z0-9_-]+)\]`
And stuff it into a folder at `codeberg/$1/$2`
Like, how cool would that be?

2026-10-16 23:55:09 UTC

Just saw something where someone called 5MHz "quite high" of a frequency,
And I don't know how I should feel that I basically consider that DC...

2026-10-14 22:31:00 UTC

mods, un-squish their catgirl

2026-10-12 07:26:04 UTC

So, i've got a question for any artist friends that "started late" as it were.
How did you manage to get over that crushing fear of failure/making "bad" art in order to actually sit down and get it done to improve and practice?
It's something i'm deeply struggling with (ignoring all my other brain issues, lamo). I just can't seem to force myself through that wall and i'm not sure how/where to start.

2026-10-03 09:41:46 UTC

math isn't the only thing about me that's poly

2026-10-02 09:38:10 UTC

The `C` in `CAD` stands for Catgirl

2026-10-02 03:51:28 UTC

I love that how fast you wiggle an electron dictates if you need to apply the arcane sigils to your circuit or not

2026-09-28 08:46:00 UTC

can't focus, got basically nothing productive done today and now I'm also feeling terribly sad out of nowhere again,
I hate it,
I just want a break
I just want to not be alone right now
I just want a future where i'm happy and not constantly worried and anxious and stressed and tired and alone

2026-09-25 16:20:51 UTC

Brain, despite needing to focus on the task in front of me, is off rolling around thinking about in-memory representations for large netlists.... please....

2026-09-25 07:33:16 UTC

her
https://assets.chaos.social/media_attachments/files/117/330/511/344/717/902/original/33b8491a4227ebcb.png

2026-09-23 01:49:16 UTC

I'm tired, and I don't want to bisect Yosys, but something between 2 weeks ago and now broke synthesis of valid designs, weh

2026-09-09 11:27:27 UTC

Still thinking about that idea I had of using the Rds_on of the load switch as a current sense resistor, lmao.

2026-09-09 09:43:41 UTC

I think it would be fun one day to work on a hardware design for something where cost is no object,
I would love to be able to use the cute AD μModule's in a design, but ough, they're so expensive, lol

2026-09-06 01:53:34 UTC

catgirl who has energy drink running through her rather than blood

2026-09-04 05:07:30 UTC

Trying to think about a way to do triggering between 4 different devices, the primary issue being lag between the primary triggering device and the device farthest away.
The easy thing is to ensure that the trigger signal is equal distance between all devices, but you still have that lag...

2026-08-20 18:16:07 UTC

https://assets.chaos.social/media_attachments/files/117/129/196/822/501/042/original/50b8cf6b8ebc666f.png

2026-08-18 08:27:47 UTC

beeeeeeeeeeeeeeeeg FPGA
https://assets.chaos.social/media_attachments/files/117/115/557/269/339/520/original/092d1908c9069a34.jpg

2026-08-17 13:01:18 UTC

Hey, random question to anyone who might have a hook up.
I'm once again looking for the documentation on the Synopsys HAPS-80D, and possibly a copy of ProtoCompiler to go with it,
If anyone has any leads let me know~ I want to get something running on my HAPS eventually, :v

2026-08-16 14:21:29 UTC

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@nprofile…mv7s The problem is the MIG itself is setting things up to have mixed Vref's per bank, and I've only really got 3 HP banks to smear the SODIMM over, seems like this is a no-win situation...

2026-08-16 14:11:34 UTC

Ugh, the Xilinx MIG and the whole nonsense with the Internal VREF and DCI chaining is giving me a headache.
Like, what do you do if a bank needs more than one Vref? bweh,

2026-08-13 20:04:58 UTC

ADHD is so cool, you'll be getting dressed out of the shower, and then suddenly it's 2 hours later and you're sitting on your bedroom floor reading a book about signal processing with nothing but your socks on...
weh.

2026-08-09 00:03:03 UTC

Ugh, I need to bitch at Xilinx about the IBIS-AMI models *AGAIN*
I should also ask them about how they expect licensing to work for CI runs.
This would be so much easier if I had a proper technical contact at AMD/Xilinx, but they refuse to do so.
It's annoying, just because i'm not buying 6-digits worth of hardware/software from them it's as if I don't exist.
Which I get, but still, at least a *little* consideration for us FOSS/OSHW players would be nice, ya know?

2026-07-28 20:37:26 UTC

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@nprofile…7k5d I wish I could get my paws on a thunderscope, the two killers for that are I don't have the money, and also I don't have any thunderbolt ports :v

2026-07-28 18:12:54 UTC

Ugh, I really need a better scope, the DS1054Z really is cute, but it's just, not enough:tm:

2026-07-24 12:18:04 UTC

1oz copper this, 2oz copper that, I'm going right to 1kg copper for my power planes 😤

2026-07-20 05:17:16 UTC

Semi-related, any of my EE friends have a good source for some high-quality, but not too expensive 50Ω SMA to BNC adapters and SMA cables?

2026-07-20 05:15:45 UTC

I think more FPGA dev boards should break out a diff-pair into just some SMA connectors on the board, not even from the SERDES (those too) but just, like, some global clock capable/LVDS IO,
It would be super useful I think.

2026-07-19 02:40:51 UTC

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@nprofile…mv7s Yeah, I'm looking for VHDL too, also spread out over every single standard, as i'm aiming on writing language frontends for all of them as fully compliant as I can.
Hence me also building up a verification suite, I know there is one (by antmicro IIRC?) for SV, but I'm targeting all standardized versions of of the "Big 3" + AMS variants.

2026-07-19 02:19:07 UTC

Question for FPGA/ASIC friends, anynyan know of a good huge collection of RTL files?
I need to build a massive corpus for profiling a language frontend, I'm thinking about seeing what I can slurp from OpenCores, but if there are pre-built corpora out there I am interested.
I'm also working on putting together an HDL standard verification suite for Verilog/SystemVerilog/Verilog-AMS/VHDL/VHDL-AMS, so eventually forming corpora for all of those would be nice.

2026-07-17 14:26:07 UTC

Remember: squishing your catgirl is an important part of their enrichment

2026-07-04 12:08:22 UTC

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@nprofile…mv7s Yeah, that was what my research came up with as well...
I guess my dream of building a high-bw sampling scope for myself is bust, booo 😔

2026-07-04 12:03:55 UTC

I am in need for a latched comparator with a 15ps rise/fall time....
Ya know, just a casual 66GHz ....

2026-07-01 18:26:05 UTC

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@nprofile…mv7s Sounds good,
Also fwiw I wasn't using a surface roughness model (mainly because I'm not 100% sure how to set it up, lmao)
I'm also on the 1b2 IRC/Discord in the eda-and-pcb channel if you rather chat about this there than on fedi

2026-07-01 18:19:03 UTC

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@nprofile…mv7s (unrelated, but I've been wanting to add ADS, and maybe even Sonnet stackup/tech export /import for the board stuff for a bit, lol,
I don't really have any access to sonnet, but I do think they have the spec for the tech file format up somewhere)

2026-07-01 18:08:14 UTC

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@nprofile…mv7s Okay, so based on what I know/have here ya go, hopefully it's enough:
https://gist.github.com/lethalbit/52bf71ae66de5e3496c6a76b8c32df53
I did double check the stackup file and I had the solder mask set to be 50um rather than what JLC said it should be at ~10um, but that didn't really change much, not sure if it's just me holding the tool wrong at this point

2026-07-01 17:52:09 UTC

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@nprofile…7k5d They want the netlists for the CI traces anyway, yeah, but i'm not sure what the numbers they are using for the calculator, if it takes into account the solder mask or not, it's really opaque, and also the stackup details for the calculator are *different* from what's on the calculator, but I emailed them and they say to go by the numbers from the order page for the stack so I have no idea

2026-07-01 17:50:11 UTC

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@nprofile…mv7s I can send you the .ltd tech file I built for the stackup if you want that,
I might not be using the ADS transmission line simulator properly, can't seem to figure out how to get it to be happy with using the soldermask.
But i'll get you the numbers properly in a second, I need to bitch at the KiCad issue tracking for causing the length tuning panel to crash PCBNew, again...

2026-07-01 17:29:52 UTC

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@nprofile…7k5d No idea, using the stackup JLC provides, the ADS transmission line simulator comes up with ~95ohm for what the JLC calculator says should be 85ohm with the same stackup.
Need to find another tool to cross-reference with,

2026-07-01 14:24:33 UTC

ugh, the JLC impedance calculator is giving me a +9.5% impedance difference to transmission line simulation,
Which is still within ±10% of the target, but that's a bit close for my liking, plus this is assuming ideal conditions, add mfr tolerances into the mix and i'm a bit more anxious about it

2026-06-30 17:06:08 UTC

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@nprofile…mv7s n-nya?

2026-06-30 16:59:51 UTC

The stackup looks kinda silly without any blind/buried Vias, lmao
https://assets.chaos.social/media_attachments/files/116/840/119/614/326/802/original/c3c8f87bef6c29be.png

2026-06-24 07:41:01 UTC

Once again, in need of a high-bw scope so I can do SerDes debugging/tweaking, ugh.

2026-06-13 18:06:33 UTC

I don't think I have any micro USB cables anymore...
I have USB-C, USB-A, USB-B, Mini-USB, but no micro...
Granted, all my USB cables *are* mixed into a box that also has my SCSI, Serial, GPIB, and Twinax cables, but still, I should have at least *one* Micro-USB.....

2026-06-09 03:12:09 UTC

If bluetooth low-energy is so good where is bluetooth high-energy,
You will surely not regret bluetooth at 150W of RF

2026-06-06 22:12:18 UTC

Apparently, just like I'm cursed to always typo `AXI` as `AKI`, I'm also cursed to always typo `bus` as `bust`....

2026-06-02 08:51:33 UTC

debating if I should bother trying to apply to oxide again, maybe for the EE role this time, even though I don't think I'm that qualified, *shrug*
Even if it does end up working out I have no idea if I can sustainably hold down a proper job, even with meds I'm not even entirely functional, bweh.

2026-05-30 09:33:06 UTC

ALSO ALSO SPEAKING OF PCIE
I think the PCI-SIG should give catgirls free membership...
SO should ISO/IEC/ITU/ANSI/T10/Si2 and SEMI 😾

2026-05-30 09:28:57 UTC

SPEAKING OF PCIE
I'm mad about `PIPE` again....
Intel absolutely massacred that poor initialism, " PHY Interface for the PCI Express, SATA, USB1, DisplayPort and USB4 Architectures", jfc,

2026-05-26 20:31:49 UTC

I love it when you try to probe some SPI lines to see what's going wrong, but the act of probing them changes the behaviour.
Ugh, maybe I need an SOIC-16 clip and not these little grabbers, but I don't /think/ i'm shorting anything together, at least not that I can see....

2026-05-18 00:17:26 UTC

Time to make catgirl soup I guess
(I'm going to take a really *really* hot bath)

2026-05-13 03:34:47 UTC

Why is it there is a bunch of resources about routing out discrete DDR modules, but nothing about (SO/R/U)DIMMs? grumpy...

2026-05-13 03:03:08 UTC

me responding to someone just now: "133MHz is pretty close to DC [...]"
I think my perspective of "fast" might be skewed a bit...

2026-05-13 01:05:28 UTC

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@nprofile…mv7s Yeah, I figure,
Let me know when hot loading/reloading for filter blocks is implemented :v

2026-05-13 00:19:41 UTC

Hi, i'm having to debug SPI Flash where the SPI transport is encapsulated in a JTAG trace from a multi-device scan-chain...

2026-05-12 16:21:56 UTC

Okay, i'm gonna bitch some more, for how fucking expensive the saleae hardware is, the software fucking sucks so much.
The decoders are absolutely *useless*, and there are so many little things that are missing that make using it miserable, death by a thousand cuts style.

2026-04-21 20:55:01 UTC

TIL that COBOL finally got the `XOR` operator in, uh, *checks notes* 2023

2026-04-18 01:54:07 UTC

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@nprofile…mv7s Yeah I figured, but field solvers are expensive and I am not very smart :v
I'm struggling enough trying to reason about the Xilinx DDR4 recommendations vs JEDECs and also just stressing about BGA escape for all the signals, a little too much for my smol brain ^^;

2026-04-18 01:41:57 UTC

Say, EE friends, this is something that I can't find a good solid answer for, but what is the clearance to a pour that turns a coplanar trace (stripline or otherwise) into a non-coplanar trace?
IIRC I read somewhere it was like 3W-5W? Or is it just the distance to the nearest reference plain?

2026-04-17 17:05:29 UTC

I don't think I will be ever able to properly mentally map Open Emitter/Open Collector to Open Drain/Open Source...
It would be nice if KiCad had a dedicated pin type for these too, because using BJT terminology for MOSFETs feels weird

2026-04-16 06:29:44 UTC

I was wondering if someone made UHV waveguides because that seems kinda like a thing that would exist, and it turns out they do!
Neat!

2026-04-16 02:56:28 UTC

this catgirl is full of pizza and thinking about clock jitter

2026-04-15 23:51:31 UTC

Would it be bad:tm: of me to use one of the signaling differential pairs in a QSFP28 cable as a power supply to a remote head?
Would basically be sticking +12V down it.....

2026-04-15 19:03:22 UTC

I am, supposedly, a professional engineer of some kind...
https://assets.chaos.social/media_attachments/files/116/410/260/835/964/276/original/835db01aa4a1f4f1.png

2026-04-08 16:39:18 UTC

Mmm, I like well organized schematics, they're hard to actually make, but sometimes you're happy with the result.
Time for walkies then I suppose...
https://assets.chaos.social/media_attachments/files/116/370/065/157/110/402/original/2701e5f2a1082e72.png

2026-04-01 01:35:32 UTC

*replaces your phones OS with OS/2*

2026-03-30 22:08:26 UTC

I'm out on walkies and I'm still trying to think of an efficient way to represent multi-level signal vectors,
And I'm a bit stunlocked at the speed vs storage tradeoffs, especially when it comes to slicing and doing logical operations on them.

2026-03-29 16:59:06 UTC

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@nprofile…7k5d It's for CI, so toolchain libraries, everything

2026-03-29 02:39:48 UTC

I still need to figure out how to properly run cross-architecture containers for CI.
Need to set up a bunch of different ones, like ppc64le, s390x, aarch64, etc but I only have an AMD64 host, and running full VMs is ough.
So gotta figure out how to get userspace container stuff working with qemu..

2026-03-20 21:53:20 UTC

Oh hey, look at that, KiCad 10 is out, which means the silly little patch I made to let bus-unfolding work with +/- suffixed signal vectors is also out~
So now `meow[0..15]+` and `meow[0..15]-` work properly~
#nevent1q…8z2h

2026-03-19 17:33:30 UTC

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@nprofile…7k5d yes

2026-03-19 16:17:39 UTC

the lost art of catgirl benchmarking

2026-03-04 07:16:21 UTC

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@nprofile…mv7s oh hey, I was just thinking about this kinda thing :v

2026-02-23 17:00:50 UTC

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@nprofile…mv7s Yeah, I'm thinking about this from a FOSS project side of things, which adds an extra layer, especially if I want to be able to use it in GitHub/GitLab/Codeberg CI

2026-02-23 16:47:25 UTC

Thinking about how to best stick Vivado/Diamond/Radiant/Quartus into something that can be used for CI
Gotta see about emailing Xilinx/Lattice/altera about licensing stuff for that, and also ough, the space T~T

2026-02-19 19:07:19 UTC

I think it's very messed up that the effectiveness of my ADHD meds, and therefore ability to focus and get work done is dependant on what I have for breakfast...
bweh,

2026-02-08 02:35:37 UTC

be gay. squish catgirls.

2026-02-01 23:30:40 UTC

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@nprofile…mv7s With how expensive RAM (and even like, fucking HDDs and SSDs, jfc) have gotten, It will likely be a loong time before I manage to scrape together an upgrade.

2026-02-01 23:26:31 UTC

whenever I manage to upgrade my machine in the future, I'm 100% going to move to ECC SDRAM, because ough,
bit-flips in very long compression tasks involving a lot of data, frighten me.

2026-01-24 22:03:08 UTC

Reading the later Verilog specs, and I wonder how much of the grammar was adjusted due to shit vendor tooling and IEEE not wanting to break compatability.
Because, jeez, there are some absolute moonbrain choices in here.

2026-01-16 05:50:48 UTC

I'm pretty sure I'm just cursed, suffering from computer toucher mana poisoning
https://assets.chaos.social/media_attachments/files/115/903/206/069/024/286/original/2abcdaa0af8c5cf3.png

2026-01-16 05:14:48 UTC

Got a git repo so wiggly that the codeberg import on it is failing, lmao.

2026-01-08 21:16:26 UTC

Was thinking last night "hey, maybe I should apply to oxide again" but, like,
I very much doubt I would be able to land the two positions I was looking at that I have even a little itty bit of experience in.
(Also my CV and work history is atrocious, RIP)
bweh,

2026-01-07 08:53:35 UTC

So, the ACM made a huge chunk of their digital library Open Access, but gated a bunch of stuff behind a "Premium" subscription, including, basic search and filtering....
So sure, you can get a bunch of papers, but you need to scroll and ^F on each page listing to try to find what you want, lol

2025-12-29 11:35:17 UTC

when in doubt, meow

2025-12-16 08:12:52 UTC

Enjoy a very poorly and hastily made meme after I almost OOM'd because of rust-analyzer again :v
https://assets.chaos.social/media_attachments/files/115/728/231/221/368/376/original/971d5e2374898222.png

2025-12-14 19:45:13 UTC

https://assets.chaos.social/media_attachments/files/115/719/633/106/617/407/original/626b99e10c89957a.png

2025-12-12 23:24:00 UTC

RFC:
❌: Request For Comments
⭕: Request For Catgirl

2025-12-10 19:52:56 UTC

Also, I want to bitch a bit again that Microchip and other silicon vendors have the data sheets for the PCIe switches and such under NDA, it's BS, I hate it.

2025-12-07 14:56:44 UTC

https://assets.chaos.social/media_attachments/files/115/678/862/566/106/539/original/048b5d98a185649d.png

2025-12-07 01:08:29 UTC

I think it should be standard issue is most homes/apartments to have a gantry crane in the main room,
Or make it easier to fit an engine hoist through the front door, that would be fine too,

2025-12-07 00:51:26 UTC

I think,
that I should be allowed to have thermal lances,
as a treat

2025-11-27 12:19:40 UTC

https://assets.chaos.social/media_attachments/files/115/621/622/207/274/735/original/37117f5ecb861c6b.png

2025-11-24 06:23:31 UTC

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@nprofile…syqt Yeah the issue here is the gate drive, need 0.6v for like, two of them, and doing aggressive BOM consolidation means I just went with a bunch of standalone ones :v

2025-11-24 06:12:30 UTC

I love playing SOT-23 & 0402 Tetris
https://assets.chaos.social/media_attachments/files/115/603/189/468/642/106/original/4d1cd5628a9d3ef8.png