There are some things that I really appreciate, and this is one of them.
> To get that throughput, I had to bit-bang all 16 lines with wur.gpio_out (8 lines per core). No room left for a clock or strobe. A CPU-driven async bus at ~100 MHz is a recipe for disaster, so the FPGA feeds the ESP its 40 MHz reference. It then follows the firmware's exact instruction timings and samples between pin transitions, with the sampling phase calibrated for the wiring.
https://www.reddit.com/r/esp32/comments/1wq37xz/got_raw_iq_streaming_out_of_an_esp32s3_at_80_mss/
Attie Grande
npub176…x772n
2026-09-30 08:55:01 UTC
Author Public Key
npub1762zhtmqez7vwesxj0m20sdpckrr2r47zqu8khlpyzntp7kzc2fsax772nSeen on
wss://relay.ditto.pubPublished at
2026-09-30 08:55:01 UTCEvent JSON
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"content": "There are some things that I really appreciate, and this is one of them.\n\n\u003e To get that throughput, I had to bit-bang all 16 lines with wur.gpio_out (8 lines per core). No room left for a clock or strobe. A CPU-driven async bus at ~100 MHz is a recipe for disaster, so the FPGA feeds the ESP its 40 MHz reference. It then follows the firmware's exact instruction timings and samples between pin transitions, with the sampling phase calibrated for the wiring.\n\nhttps://www.reddit.com/r/esp32/comments/1wq37xz/got_raw_iq_streaming_out_of_an_esp32s3_at_80_mss/",
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